收藏本站
78M6610+PSU Data Sheet
Bus Characteristics
?
?
A data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Bus Conditions:
?
?
?
?
?
Bus not Busy (I): Both data and clock lines are HIGH indicating an Idle Condition.
Start Data Transfer (S): a HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH
determines a START condition. All commands must be preceded by a START condition.
Stop Data Transfer (P): a LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH
determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid: The state of the data line represents valid data when, after a START condition, the data
line is stable for the duration of the HIGH period of the clock signal. The data on the line must be
changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each
data transfer is initiated with a START condition and terminated with a STOP condition.
Acknowledge (A): Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse, which is
associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH
period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into
account. During reads, a master must signal an end of data to the slave by not generating an
Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave
(78M6610+PSU) will leave the data line HIGH to enable the master to generate the STOP condition.
SDA
MSB
SCL
1
2
7
8
9
ACK
9
ACK
Start Bit
SCL may be held low by
slave to service interrupts
Start or Stop Bits
Device Addressing
A control byte is the first byte received following the START condition from the master device.
The control byte consists of a seven bit address and a bit (LSB) indicating the type of access (0=write;
1=read).
DEVICE ADDRESS
LSB
MSB
S
X
X
X
X
X
X
X
R/W ACK
START BIT
50
READ/WRITE
ACKNOWLEDGE
Rev 1
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
78M6612-DB/OMU-USB KIT DEMO OUTLET MEASUREMENT OMU1
78M6612-EVM-1 BOARD EVAL 78M6612 AC-PMON
78M6613-EVM-1 EVAL BOARD 78M6613
78M6613-SP-1 EVAL KIT 78M6613-SP-1
78M6618-PDU1 BOARD EVAL 78M6618 PDU1
78M6631-EVM-1 EVAL BOARD 78M6631
78P2351R-DB BOARD DEMO FOR 78P2351R
79-WHITE-1"X60YD TAPE GLASS CLOTH 1"X 60YD WHT
相关代理商/技术参数
78M6610+PSUEVK1# 制造商:Maxim Integrated Products 功能描述:ENERGY MEASUREMENT PROCESSOR EV KIT FOR SINGLE-PHASE POWER-S - Boxed Product (Development Kits) 制造商:Maxim Integrated Products 功能描述:EVAL KIT 78M6610+PSU
78M6610LMU 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Energy Measurement Processor for Load Monitoring Units
78M6611-EVM 制造商:Maxim Integrated Products 功能描述:78M6611 EVAL BOARD - Boxed Product (Development Kits)
78M6611-IVT/F 功能描述:IC POWER MEASUREMENT AC 24-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:*
78M6611-IVT/F/P 制造商:Maxim Integrated Products 功能描述:PROGRAMMED - LEAD FREE - Rail/Tube
78M6611-IVTR/F 功能描述:IC POWER MEASUREMENT AC 24-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:*
78M6611-IVTR/F/P 制造商:Maxim Integrated Products 功能描述:PROGRAMMED - LEAD FREE/TAPE & REEL - Tape and Reel
78M6612 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Single-Phase, Dual-Outlet Power and Energy Measurement IC